Resources
Xilinx Hardware & Design Tools
7 Series Product Tables and Product Selection Guide (XMP101): The last page contains links to the most important user guides (CLBs, rams, DSPs, IOs, …)
Vivado Design Suite User Guide: Synthesis (UG901): HDL templates for inferring block rams (inferring as (simpler) alternative to instantiate library primitives). Only works for Vivado.
Vivado Design Suite 7 Series FPGA and Zynq-7000 SoC Libraries Guide UG953 (v2021.2) October 22, 2021: Instance templates for all library primitives
Digilent Nexys Video FPGA Board
RISC-V System
OpenTitan’s Reggen manual (differs in details from the version used in rvlab!)
OpenTitan’s Crossbar Generation tool manual (differs in details from the version used in rvlab!)
SystemVerilog
Verilog Language reference manual (LRM) (the authoritative source to consult for in depth questions, e.g. how a certain language element is to be handeled by a simulator).
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The tutorial From Blinky to RISC-V starts with the Verilog of a single blinking LED and extends this step by step ending with a minimal but functional RISC-V core (running DOOM!). Verilog, but can be easily adapted to SystemVerilog.
External IP
Could be useful (i.e. no guarantee) for student projects.
Built in previous rvlabs:
HDMI input
rvlab 2024 project: DVI/HDMI input for the Artix-7 FPGA with TileLink interface
Xilinx application note explaining basic concept: Implementing a TMDS Video Interface in the Spartan-6 FPGA
External:
GBit Ethernet MAC (used in rvlab 2023): verilog-ethernet
HDMI output
basic explanation & (overly simplified - do not use) implementation: fpga4fun
DVI only, no sound: display_controller
HDMI, with sound: hdmi