RISC-V Lab
Contents:
Design Reference
Tutorials
Setup
Design Flow Recipes
Software
FPGA Upload
GitLab CI Pipeline
Resources
RISC-V Lab
Tutorials
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Tutorials
Contents:
Setup
Support status
Install open-source components
Install Xilinx Vivado (proprietary)
Install Questa-Intel (proprietary)
Example Setup
Design Flow Recipes
Module Simulation
System Simulation
FPGA Implementation (Synthesis, Place and Route)
Netlist Simulation
Adding module-level testbenches
Extending the crossbar switches
Behind the scenes
Software
Adding programs
Host I/O
Initializing DDR3
Dynamic memory management
FPGA Upload
Load bitstream
Run software
Debug via GDB
GitLab CI Pipeline