Design Flow Reference
The following reference list of defined targets is automatically generated from the blocks instantiated in flow/__init__.py and defined in the flow/*.py files.
Please check Design Flow Recipes for how to use the design flow.
- block libsys
Shared system library including a small libc providing basic system functions such as printf, memcpy etc.
- target libsys.build
- Requires:
Builds library for static linking (.a).
- block sw_monitor
Program for the RISC-V CPU
- always_rebuild target sw_monitor.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_monitor.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_monitor.delta
- Requires:
Differential image for fast loading in simulator
- block sw_minimal
Program for the RISC-V CPU
- always_rebuild target sw_minimal.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_minimal.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_minimal.delta
- Requires:
Differential image for fast loading in simulator
- block sw_test_sim_ddr
Program for the RISC-V CPU
- always_rebuild target sw_test_sim_ddr.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_test_sim_ddr.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_test_sim_ddr.delta
- Requires:
Differential image for fast loading in simulator
- block sw_test_rvlab
Program for the RISC-V CPU
- always_rebuild target sw_test_rvlab.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_test_rvlab.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_test_rvlab.delta
- Requires:
Differential image for fast loading in simulator
- block sw_coremark
Program for the RISC-V CPU
- always_rebuild target sw_coremark.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_coremark.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_coremark.delta
- Requires:
Differential image for fast loading in simulator
- block sw_test_irq
Program for the RISC-V CPU
- always_rebuild target sw_test_irq.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_test_irq.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_test_irq.delta
- Requires:
Differential image for fast loading in simulator
- block sw_rlight
Program for the RISC-V CPU
- always_rebuild target sw_rlight.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_rlight.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_rlight.delta
- Requires:
Differential image for fast loading in simulator
- block sw_dma
Program for the RISC-V CPU
- always_rebuild target sw_dma.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_dma.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_dma.delta
- Requires:
Differential image for fast loading in simulator
- block sw_project
Program for the RISC-V CPU
- always_rebuild target sw_project.build
- Requires:
Main program for simulation and later use on FPGA.
- target sw_project.run
- Requires:
Run on FPGA via OpenOCD
- always_rebuild target sw_project.delta
- Requires:
Differential image for fast loading in simulator
- block xbar
Crossbar switch generator using OpenTitan’s tlgen
- target xbar.generate
Generate SystemVerilog sources
- block reggen
Register generator using OpenTitan’s reggen
- target reggen.generate
Generate SystemVerilog + C headers
- block simlibs_questa
Xilinx simulation cell libraries for QuestaSim
- target simlibs_questa.unisims
Library for functional simulation
- target simlibs_questa.simprims
Library for timing-annotated netlist simulation
- target simlibs_questa.secureip
Encrypted simulation model library
- block ddr3_model
Obtain simulation model of DDR3 chip.
- target ddr3_model.generate
Generate SystemVerilog + C headers
- block srcs
Hardware sources
- always_rebuild target srcs.srcs_noddr
- Requires:
RTL + verification sources without DDR3
- always_rebuild target srcs.srcs
- Requires:
RTL + verification sources including DDR3
- target srcs.lint
- Requires:
Run static code quality assessment
- block rvlab_fpga_top
Top-level FPGA design
- target rvlab_fpga_top.pnr
- Requires:
Place and route netlist
- target rvlab_fpga_top.slack_analysis
- Requires:
Slack histogram to inspect timing using Vivado GUI
- target rvlab_fpga_top.bitstream
- Requires:
Generate bitstream from PNR result
- target rvlab_fpga_top.program
- Requires:
Load bitstream to FPGA
- block student_rlight_tb
Module-level testbench
- target student_rlight_tb.sim_rtl_questa
- Requires:
RTL simulation with QuestaSim
- target student_rlight_tb.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim, including libraries required for simulating the DDR3 model
- target student_rlight_tb.sim_rtl_questa_batch
- Requires:
RTL simulation with QuestaSim (batch mode)
- target student_rlight_tb.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- block student_tlul_mux_tb
Module-level testbench
- target student_tlul_mux_tb.sim_rtl_questa
- Requires:
RTL simulation with QuestaSim
- target student_tlul_mux_tb.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim, including libraries required for simulating the DDR3 model
- target student_tlul_mux_tb.sim_rtl_questa_batch
- Requires:
RTL simulation with QuestaSim (batch mode)
- target student_tlul_mux_tb.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- block systb_monitor
System testbench
- target systb_monitor.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_monitor.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_monitor.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_monitor.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_monitor.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_monitor.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_monitor.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_monitor.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_monitor.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_minimal
System testbench
- target systb_minimal.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_minimal.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_minimal.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_minimal.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_minimal.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_minimal.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_minimal.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_minimal.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_minimal.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_test_sim_ddr
System testbench
- target systb_test_sim_ddr.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_test_sim_ddr.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_test_sim_ddr.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_test_sim_ddr.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_test_sim_ddr.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_test_sim_ddr.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_test_sim_ddr.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_test_sim_ddr.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_test_sim_ddr.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_test_rvlab
System testbench
- target systb_test_rvlab.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_test_rvlab.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_test_rvlab.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_test_rvlab.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_test_rvlab.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_test_rvlab.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_test_rvlab.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_test_rvlab.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_test_rvlab.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_coremark
System testbench
- target systb_coremark.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_coremark.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_coremark.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_coremark.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_coremark.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_coremark.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_coremark.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_coremark.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_coremark.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_test_irq
System testbench
- target systb_test_irq.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_test_irq.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_test_irq.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_test_irq.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_test_irq.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_test_irq.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_test_irq.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_test_irq.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_test_irq.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_rlight
System testbench
- target systb_rlight.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_rlight.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_rlight.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_rlight.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_rlight.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_rlight.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_rlight.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_rlight.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_rlight.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_dma
System testbench
- target systb_dma.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_dma.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_dma.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_dma.sim_synfunc_questa
-
Post-synthesis functional simulation with QuestaSim
- target systb_dma.sim_pnrtime_questa
-
Post-PNR timing simulation with QuestaSim
- target systb_dma.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_dma.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_dma.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_dma.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim
- block systb_project
System testbench
- target systb_project.sim_rtl_questa
-
RTL simulation with QuestaSim
- target systb_project.sim_rtl_questa_ddr
-
RTL simulation with QuestaSim including DDR3
- target systb_project.sim_rtl_questa_batch
-
RTL simulation with QuestaSim (batch mode)
- target systb_project.sim_synfunc_questa
- Requires:
Post-synthesis functional simulation with QuestaSim
- target systb_project.sim_pnrtime_questa
- Requires:
Post-PNR timing simulation with QuestaSim
- target systb_project.sim_rtl_xsim
- Requires:
RTL simulation with XSim
- target systb_project.sim_rtl_xsim_ddr
- Requires:
RTL simulation with XSim including DDR3
- target systb_project.sim_synfunc_xsim
- Requires:
Post-synthesis functional simulation with XSim
- target systb_project.sim_pnrtime_xsim
- Requires:
Post-PNR timing simulation with XSim